The present invention relates to a phase synchronous device, and more precisely to a phase synchronous device for improving jitter of an output signal and a method for generating a phase synchronous signal.
In general, most circuits include clock circuits for high-speed operation, such as a phase locked loop (hereinafter, referred to as a “PLL”) and a delay locked loop (hereinafter, referred to as a “DLL”).
Meanwhile, each of the PLL and DLL includes a phase detector, a charge pump, a loop filter and a voltage controller.
In each of the PLL and DLL, the phase detector compares the phases of first and second signals with each other to generate first and second pulses corresponding to a difference between the phases of the first and second signals.
Here, the first signal is a reference input signal, and the second signal is a feedback output signal. In the PLL, the first and second signals are frequency signals. In the DLL, the first and second signals are clock signals.
The first pulse is a pull-up pulse and activated when the phase of the second signal is lagged with respect to that of the first signal. The second pulse is a pull-down pulse and activated when the phase of the second signal is led with respect to that of the first signal. When the phases of the first and second signals are locked, the first and second pulses are simultaneously activated during a short interval.
The charge pump drives PMOS and NMOS transistors respectively corresponding to the first and second pulses so as to pump a current.
The loop filter charges/discharges the current to output a control voltage.
The voltage controller controls the phase of the second signal corresponding to the control voltage and then outputs an output signal.
Such an operation is repeatedly performed until the phases of the first and second signals approach within a predetermined range to be locked.
In each of the PLL and DLL, when the phases of the first and second signals are locked, the first and second pulses are simultaneously activated during a short interval. At this time, a peak current having a current difference is generated due to the mismatch in current driving capabilities of the PMOS and NMOS transistors constituting the charge pump.
Since such a peak current flows in the range of a few hundreds μA to a few μA even a reference current is a few mA, the charge pump causes a difference between amounts of currents flowing through the PMOS and NMOS transistors.
As a result, there is a problem in that, when the phases of the first and second signals is locked, a control voltage output from the loop filter is unstable, and thus jitter is produced in the second signal controlled by the voltage controller.